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IS31FL3730 integrated silicon solution, inc. ? www.issi.com 1 rev.a, 12/19/2011 audio modulated matrix led driver december 2011 general description IS31FL3730 is a led matrix driver which features an audio modulation display mode and a general led dot matrix display mode. the default configuration of IS31FL3730 is to drive a single 88 led matrix. however, IS31FL3730 may be configured to drive either one or two 88, 79, 610, or 511 dot matrix display(s). the intensity of any matrix picture can be modulated by an audio signal. in matrix display mode, the rows and columns of the matrix are internally scanned, requiring only one time programming of the individual led on or off state, thus eliminating the need for real time system resource utilization to perform the row and column scanning function. in the general purpose mode, the on or off condition of each individual led in the display matrix is programmed via an i2c interface. IS31FL3730 is available in qfn-24 (4mm 4mm). it operates from 2.7v to 5.5v over the temperature range of -40c to +85c. features ? 2.7v to 5.5v supply ? i2c interface, automatic address increment function ? internal reset register ? programmable single or dual 88, 79, 610, or 511 led matrix display mode ? one-time programming, internal scan ? audio modulated display intensity with digitally programmable input gain ? internal registers to digitally adjust display intensity ? modulate led brightness with 128 different items in pwm ? one address pin with 4 logic levels to allow four i2c slave addresses ? over-temperature protection ? qfn-24 (4mm 4mm) package applications ? mobile phones and other hand-held devices for led display ? led in home appliances typical application circuit figure 1 typical application circuit dual 88 note: the ic should be placed far away from the mobile antenna in order to prevent the emi.
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 2 rev.a, 12/19/2011 figure 2 typical application circuit dual 79 figure 3 typical application circuit dual 610 figure 4 typical application circuit dual 511
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 3 rev.a, 12/19/2011 pin configuration package pin configuration (top view) qfn-24 pin description no. pin description 1 sda i2c serial data. 2 scl i2c serial clock. 3 sdb shutdown the chip when pull to low. 4 in audio input. 5 c_filt filter cap for audio control. 6 ad i2c address setting. 7~10, 12 r1~r5 row control. 11 vcc power supply. 13~15 r6/c11, r7/c10, r8/c9 row/column control. 16~19, 21~24 c8~c5, c4~c1 column control. 20 gnd ground. thermal pad connect to gnd. copyright ? ? ? 2011 ? integrated ? silicon ? solution, ? inc. ? all ? rights ? reserved. ? issi ? reserves ? the ? right ? to ? make ? changes ? to ? this ? specification ? and ? its ? products ? at ? any ? time ? without ? notice. ? issi ? assumes ? no ? liability ? arising ? out ? of ? the ? application ? or ? use ? of ? any ? information, ? products ? or ? services ? described ? herein. ? customers ? are ? advised ? to ? obtain ? the ? latest ? version ? of ? this ? device ? specification ? before ? relying ? on ? any ? published ? information ? and ? before ? placing ? orders ? for ? products. ? integrated ? silicon ? solution, ? inc. ? does ? not ? recommend ? the ? use ? of ? any ? of ? its ? products ? in ? life ? support ? applications ? where ? the ? failure ? or ? malfunction ? of ? the ? product ? can ? reasonably ? be ? expected ? to ? cause ? failure ? of ? the ? life ? support ? system ? or ? to ? significantly ? affect ? its ? safety ? or ? effectiveness. ? products ? are ? not ? authorized ? for ? use ? in ? such ? applications ? unless ? integrated ? silicon ? solution, ? inc. ? receives ? written ? assurance ? to ? its ? satisfaction, ? that: ? a.) ? the ? risk ? of ? injury ? or ? damage ? has ? been ? minimized; ? b.) ? the ? user ? assume ? all ? such ? risks; ? and ? c.) ? potential ? liability ? of ? integrated ? silicon ? solution, ? inc ? is ? adequately ? protected ? under ? the ? circumstances
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 4 rev.a, 12/19/2011 ordering information industrial range: -40c to +85c order part no. package qty/reel IS31FL3730-qfls2-tr qfn-24, lead-free 2500
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 5 rev.a, 12/19/2011 absolute maximum ratings supply voltage, v cc - 0.3v ~ +6.0v voltage at any input pin - 0.3v ~ v cc +0.3v maximum junction temperature, t jmax 150c storage temperature range, t stg - 65c ~ +150c operating temperature range, t a ? 40c ~ +85c note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the sp ecifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics t a = -40c to +85c, v cc =2.7v to 5.5v, unless otherwise noted. typical value are t a = 25c, v cc = 3.6v. symbol parameter condition min. typ. max. unit v cc supply voltage 2.7 5.5 v i cc quiescent power supply current v in = 0v, without audio input, all leds off 7.0 ma i sd shutdown current v sdb = 0v 0.2 1.0 a v sdb = v cc , software shutdown 1.7 3.0 i out output current of r1~r8, c1~c8 matrix display mode without audio modulation lighting effect register(0dh) = 0xxx 0000 40 (note 1) ma matrix display mode with audio modulation v in =2.5v p-p , 1khz square wave audio gain = 0db 40 (note 1) v hr current sink headroom voltager1~r8,c1~c8 i sink = 320ma (note 2) 300 mv current source headroom voltage r1~r8,c1~c8 i source = 40ma 200 t scan period of row and column scanning (figure 10) 32 s t scanol non-overlap blanking time during row and column scan (figure 10) 1 s logic electrical characteristics (sda, scl, ad) v il logic ?0? input voltage v cc = 2.7v 0.4 v v ih logic ?1? input voltage v cc = 5.5v 1.4 v i il logic ?0? input current v in = 0v 5 (note 3) na i ih logic ?1? input current v in = v cc 5 (note 3) na
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 6 rev.a, 12/19/2011 digital input switching characteristics (note 3) symbol parameter condition min. typ. max. units f scl serial-clock frequency 400 khz t buf bus free time between a stop and a start condition 1.3 s t hd, sta hold time (repeated) start condition 0.6 s t su, sta repeated start condition setup time 0.6 s t su, sto stop condition setup time 0.6 s t hd, dat data hold time 0.9 s t su, dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.7 s t r rise time of both sda and scl signals, receiving (note 4) 20+0.1cb 300 ns t f fall time of both sda and scl signals, receiving (note 4) 20+0.1cb 300 ns note 1: due to the row and column scanning sequence, the average current of an individual led in the display is iout/8 when configured to drive a single matrix. when configured to drive two matrices, the average current of an individual led in the display is iout/1 6. note 2: all row drivers are on. note 3: guaranteed by design. note 4: cb = total capacitance of one bus line in pf. isink 6ma. tr and tf measured between 0.3 v cc and 0.7 v cc .
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 7 rev.a, 12/19/2011 detailed description i2c interface the IS31FL3730 uses a serial bus, which conforms to the i2c protocol, to control the chip?s functions with two wires: scl and sda. the IS31FL3730 has a 7-bit slave address (a7:a1), followed by the r/w bit, a0. since IS31FL3730 only supports write operations, a0 must always be 0. the value of bits a1 and a2 are decided by the connection of the ad pin. the complete slave address is: table1 slave address (write only): bit a7:a3 a2:a1 a0 value 11000 ad 0 ad connected to gnd, ad=00; ad connected to vcc, ad=11; ad connected to scl, ad=01; ad connected to sda, ad=10; the scl line is uni-directional. the sda line is bi-directional (open-collector) with a pull-up resistor (typically 4.7k ? ). the maximum clock frequency specified by the i2c standard is 400khz. in this discussion, the master is the microcontroller and the slave is the IS31FL3730. the timing diagram for the i2c is shown in figure 5. the sda is latched in on the stable high level of the scl . when there is no interface activity, the sda line should be held high. the ?start? signal is generated by lowering the sda signal while the scl signal is high. the start signal will alert all devices attached to the i2c bus to check the incoming address against their own chip address. the 8-bit chip address is sent next, most significant bit first. each address bit must be stable while the scl level is high. after the last bit of the chip address is sent, the master checks for the IS31FL3730?s acknowledge. the master releases the sda line high (through a pull-up resistor). then the master sends an scl pulse. if the IS31FL3730 has received the address correctly, then it holds the sda line low during the scl pulse. if the sda line is not low, then the master should send a ?stop? signal (discussed later) and abort the transfer. following acknowledge of IS31FL3730, the register address byte is sent, most significant bit first. IS31FL3730 must generate another acknowledge indicating that the register address has been received. then 8-bit of data byte are sent next, most significant bit first. each data bit should be valid while the scl level is stable high. after the data byte is sent, the IS31FL3730 must generate another acknowledge to indicate that the data was received. the ?stop? signal ends the transfer. to signal ?stop?, the sda signal goes high while the scl signal is high. address auto increment to write multiple bytes of data into IS31FL3730, load the address of the data register that the first data byte is intended for. during the IS31FL3730 acknowledge of receiving the data byte, the internal address pointer will increment by one. the next data byte sent to IS31FL3730 will be placed in the new address, and so on. the auto increment of the address will continue as long as data continues to be written to IS31FL3730. this feature is useful for loading the led on/off condition for each of the display matrices as a burst of data. pay careful attention when loading data for dual led matrix displays since the register addressing is not continuous. figure 5 interface timing data line stable; data valid change of data allowed scl sda figure 6 bit transfer
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 8 rev.a, 12/19/2011 figure 7 writing to IS31FL3730(typical) figure 8 writing to IS31FL3730(automatic address increment) register definition table2 register function address name function tab l e default 00h configuration register set operation mode of IS31FL3730 3 0000 0000 01h~0bh matrix 1 data register store the on or off state of each led 4 0000 0000 0eh~18h matrix 2 data register store the on or off state of each led 5 0ch update column register make the data register update the data - xxxx xxxx 0dh lighting effect register store the intensity control settings 6 0000 0000 19h pwm register modulate led light with 128 different items 7 1000 0000 ffh reset register reset all registers to default value - xxxx xxxx table3 00h configuration register bit d7 d6:d5 d4:d3 d2 d1 d0 name ssd reserved dm a_en adm default 0 00 00 0 0 0 the configuration register sets operation mode of IS31FL3730. ssd software shutdown enable 0 normal operation 1 software shutdown mode dm display mode 00 matrix 1 only 01 matrix 2 only 11 matrix 1 and matrix 2 a_en audio input enable 0 matrix intensity is controlled by the current setting in the lighting effect register (0dh) 1 enable audio signal to modulate the intensity of the matrix adm matrix mode selection 00 88 dot matrix display mode 01 79 dot matrix display mode 10 610 dot matrix display mode 11 511 dot matrix display mode
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 9 rev.a, 12/19/2011 table4 01h~0bh matrix 1 data register(c1~c11) bit d7:d0 name r8:r1 default 00000000 table5 0eh~18h matrix 2 data register(c1~c11) bit d7:d0 name r8:r1 default 00000000 the data registers (matrix 1/matrix 2) store the on or off state of each led in the matrix. rx led state 0 led off 1 led on 112 registers are assigned to c1~c11 columns respectively; the led at a particular (row, column) location will be turned on when the respective data is set to ?1?. when configured for more than 8 column operation, only the required numbers of lsbs are used in each data register. for example, in 511 dot matrix mode, only bits r1 thru r5 are used, and bits r6 thru r8 are ignored. 0ch update column register the data sent to the data registers will be stored in temporary registers. a write operation of any 8-bit value to the update column register is required to update the data registers (01h~0bh, 0eh~18h). table6 0dh lighting effect register bit d7 d6:d4 d3:d0 name reserved ags cs default 0 000 0000 the lighting effect register stores the intensity control settings for all of the leds in the matrix. ags audio input gain selection 000: gain= 0db 001: gain= +3db 010: gain= +6db 011: gain= +9db 100: gain= +12db 101: gain= +15db 110: gain= +18db 111: gain= -6db cs full current setting for each row output 0000: 40ma 0001: 45ma ... ... 0111: 75ma 1000: 5ma 1001: 10ma ... ... 1110: 35ma table7 19h pwm register bit d7 d6:d0 default 1 0000000 the pwm register can modulate led light with 128 different items. when the d7 set to ?1?, the pwm is the 128 item. when the d7 set to ?0?, d6:d0 set the pwm from the 0 item to the 127 item. for example, if the data in pwm register is 0000 0100, then the pwm is the 4 item. figure 9 pwm timing diagram ffh reset register once user writes any 8-bit data to the reset register, IS31FL3730 will reset all registers to default value. on initial power-up, the IS31FL3730 registers are reset to their default values for a blank display.
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 10 rev.a, 12/19/2011 application information general purpose dot matrix display mode the general purpose dot matrix display timing diagram is shown in figure 10. IS31FL3730 may be configured to drive displays of different dimensions from 88 to 511. furthermore, IS31FL3730 may be configured to drive one or two led matrices of the same dimension. therefore, the overall row and column scan time can vary based on the final led matrix configuration. in any led matrix configuration, a single line (column or row) of leds is illuminated for 32s before IS31FL3730 moves on to the next line of leds (figure 10). example 1: when the IS31FL3730 is configured in the general purpose dual 88 dot matrix display mode, column controls c8:c1 scans the eight columns of matrix 1 then row controls r8:r1 scans the eight rows of matrix 2 at a rate of 1.89khz, or 528s per frame. each line is active for 32s. the non-overlap interval between adjacent lines is 1s. example 2: when configured to drive a single 79 dot matrix display (matrix 1), the column controls c9:c1 scan the nine columns every 297s. also note that in this case, the data registers? msb will be ignored. figure 10 dot matrix display timing diagram dual 8 8 dot matrix display mode the application example in figure 1 shows the IS31FL3730 in the dual 88 led dot matrix display mode. the matrix 1 led columns have common cathodes and are connected to the c1:c8 outputs. the rows are connected to the row drivers. the matrix 2 led rows have common cathodes and connected to the r1:r8. the columns are connected to the c1:c8. each of the 128 leds can be addressed separately. dual 5 11 dot matrix display mode by setting the adm bits of the configuration register (00h) to ?11? and the dm bits to ?11?, the IS31FL3730 will operate in the dual 511 led dot matrix display mode. the matrix 1 led columns have common cathodes and are connected to the c1:c11 outputs. the rows are connected to the row drivers. the matrix 2 led rows have common cathodes and are connected to the r1:r5 outputs. the columns are connected to the column drivers. each of the 110 leds can be addressed separately. the three msbs (d7:d5) of each data register (01h~0bh, 0eh~18h) are ignored. dot matrix display mode with audio modulation when the IS31FL3730 operates in any of the dot matrix modes, if the bit a_en in configuration register (00h) is set to ?1?, the brightness of led image can be modulated by audio signal not controlled by the cs bit in lighting effect register (0dh). an external capacitor, c_filt is required to control the rate at which the display in tensity will change. the rate of change is computed using the formula: ? t = c500k ? . a value of 0.1f provides a good effect by allowing the display to fade from full intensity to off in approximately 50ms. smaller capacitance will cause the intensity to change more quickly, and, conversely, a larger capacitance will cause the display intensity to change at a slower rate. shutdown mode shutdown mode can either be used as a means of reducing power consumption or generating a flashing display (repeatedly entering and leaving shutdown mode). during shutdown mode all registers retain their data. software shutdown by setting ssd bit of the configuration register (00h) to ?1?, the IS31FL3730 will operate in software shutdown mode, wherein they consume only 1.7 a (typ.) current. when the IS31FL3730 is in software shutdown mode, all current sources and digital drivers are switched off, so that the matrix is blanked. hardware shutdown the chip enters hardware shutdown mode when the sdb pin is pulled low.
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 11 rev.a, 12/19/2011 classification reflow profiles profile feature pb-free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60-120 seconds average ramp-up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60-150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp-down rate (tp to tsmax) 6c/second max. time 25c to peak temperature 8 minutes max. figure 11 classification profile
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 12 rev.a, 12/19/2011 tape and reel information
IS31FL3730 integrated silicon solution, inc. ? www.issi.com 13 rev.a, 12/19/2011 package information qfn-24 note: all dimensions in millimeters unless otherwise stated.

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